IPC-J-STD-012: Implementation of Flip Chip & Chip Scale Technology

Member: $84.00

Nonmember: $168.00

This informative document describes the implementation of flip chip and related chip scale semiconductor packaging technologies. The areas discussed include design considerations, assembly processes, technology choices, application and reliability data. Chip packaging variations include flip chip, HDI, micro BGA, micro SMT and SLICC. Also provides general information on implementing flip chip and chip scale technologies for creating multichip modules, I/C cards, memory cards and very dense surface mount assemblies. Developed by IPC, EIA, MCNC and Sematech. 113 Pages. Released January 1996.

Equivalent to IEC Publicly Available Standard (PAS) 6208

Product ID: J012-STD-0-D-0-EN-0