This popular document covers land pattern design for all types of passive and active components, including resistors, capacitors, MELFs, SOPs, QFPs, BGAs, QFNs and SONs. The standard provides printed board designers with an intelligent land pattern naming convention, zero component rotations for CAD systems and three separate land pattern geometries for each component that allow the user to select a land pattern based on desired component density.
Revision B now includes land pattern design guidance and rules for component families such as resistor array packages, aluminum electrolytic capacitors, column and land grid arrays, flat lead devices (SODFL and SOTFL) and dual flat no-lead (DFN) devices. The revision also discusses the usage of thermal tabs and provides a new padstack naming convention that addresses the shape and dimensions of lands on different layers of printed boards.
The IPC Land Pattern Calculator is no longer included as of Oct. 1, 2017