Current Revision
A-36-Gerber0G

A-36: Surface Insulation Resistance

This double-sided test board has ten SIR test patterns which were designed for the IPC cleanliness test program, Phase 1 to examine the ability of a cleaning solvent to remove flux residues and the effects of entrapped residues under low standoff components. The PCB-B-36 test board can be used as a process qualification vehicle for the J-STD-001 which references IPC-9201. The test patterns consist of four comb patterns with 6 mil lines/spaces, two SMT pads 25 mil spaces, two inner perimeter patterns with 6 mil lines/spaces, and two outer perimeter patterns with 6 mil lines/spaces. The contact fingers of the board are normally gold plated for compatibility with edge card connectors with the remaining metallization of bare copper when used for qualification but can be other surface finishes. In most cases, four leadless ceramic chip carriers (LCCs) are mounted on the board, one in each quadrant. This test vehicle is designed to test combinations of conformal coatings, fluxes, solder paste and their interactions with each other as well as to test the removal of cleaning residues under low stand-off components. .

Published Date
DoD Adopted
No
ANSI Approved
No