EIA/IPC/JEDEC J-STD-075 picks up where J-STD-020 left off by providing test methods to classify worst-case thermal process limitations for electronic components. Classification is referenced to common industry wave and reflow solder profiles including lead-free processing. The classifications represent maximum process sensitivity levels and do not establish rework conditions or recommended...
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IPC-7352: Generic Guideline for Land Pattern Design
IPC-4922: Requirements for Sintering Materials for Electronics Assembly
IPC-2591, Version 1.6: Connected Factory Exchange (CFX)
J-STD-005B: Requirements for Soldering Pastes
IPC-1791C: Trusted Electronic Designer, Fabricator and Assembler Requirements